TIM1 fM Clock

UUID: BB2BD987-A43C-4B7E-8A7B-5389C5155CF2

The master-clock timing function shall generate the detector fM signal at 2 MHz +/- 0.1%. Pin assignment, timer channel, divisor, duty-cycle tolerance, startup behavior, and whether the signal is continuous in every controller state are Not In Docs.

Expected outcome: A powered, enabled acquisition path presents a stable fM waveform at the detector interface within the 2 MHz +/- 0.1% acceptance tolerance.